1. Field of the Invention
The present invention relates to a logic circuit, a logic circuit design method, a logic circuit design system, and a logic circuit design program, and particularly relates to a logic circuit, a logic circuit design method, a logic circuit design system, and a logic circuit design program, in which a predetermined basic logic circuit is converted into a latch circuit, and with which a high-speed operation is achieved.
2. Description of the Related Art
To constitute a sequential circuit using a plurality of basic logic circuits, a pipeline method is employed in which, for example, a flip-flop is inserted between one basic logic circuit and the next basic logic circuit. According to a conventional logic circuit design method, a sequential circuit is divided on the basis of a target cycle time, and a flip-flop is inserted between the basic logic circuits. The output of a specific basic logic circuit is held by the flip-flop, and is also inputted to the next basic logic circuit. In this manner, a pipeline is conventionally formed by the insertion of the flip-flop.
To drive the flip-flop, a clock signal is employed. For the distribution of the clock signal, it is necessary to consider clock skew, which is the spatial disproportion of distribution delays and variations in, for example, jitter, which is a time fluctuation. The overhead for the variations in the skew, the jitter or the like reduces the effective cycle time. And especially for high-speed LSIs, there arises a problem that system performance is degraded.
To resolve the problem of the reduction in the effective cycle time due to such skew and jitter, a latch circuit design technique has been proposed that corresponds to the pipeline design for high-speed LSIs. For example, the basic concept for the design of a latch circuit is proposed in Japanese Laid-Open Patent No. 2001-156598 and in David Harris, et al., “Skew-tolerant Domino Circuits”, ISSCC 1997 Digest of Technical Papers, pp. 422–423.
However, only the basic circuit design concept for the arrangement, in a circuit to be designed, of latch circuits is described in these documents, which in addition, provide no description of the configuration of a definite latch circuit and of a design method for a target circuit.
For example, according to Japanese Laid-Open Patent No. 2001-156598, clock signal supply means supplies a common clock signal to an input flip-flop circuit, an output flip-flop circuit and a latch circuit, which jointly act as a pipeline having two or more stages. Further, circuit insertion position determination means determines the position whereat the input flip-flop circuit and the output flip-flop circuit, or the latch circuit, are to be inserted, so that the input for the latch circuit is established in the middle of the through period for the latch circuit. In this way, the insertion position is determined by the circuit insertion position determination means, so that the influence on a multi-stage pipeline latch circuit exerted by skew due to a variation in transistor performance is minimized. For the similar reason, the influence on the multi-stage pipeline latch circuit is minimized with respect to the variation of the duty ratio or the like or the jitter caused when the LSI is in operation. In this document, it is stated that, as a result, the operation of an LSI product is stabilized.
Meanwhile, according to Japanese Laid-Open Patent No. 2004-056238, means for determining a flip-flop to be converted into a latch selects a flip-flop which is not to be converted into a latch, and then, latch conversion means converts, into a latch circuit having a through state wherein the output side can borrow the delay margin originating on the input side, the flip-flop which is not selected by the means for determining a flip-flop to be converted into a latch. Thus, the delay in the flip-flop output, the setup time and the clock skew can be reduced. Further, in this document, it is stated that it becomes possible to convert all the flip-flops, for example, flip-flops which do not have a delay margin on the input into latch circuits.
However, according to the conventional latch circuit design method described above, neither the configuration of a latch circuit which is appropriate for latch circuit design nor a circuit design method for converting a logic circuit into a latch circuit are proposed.